The present invention relates to a data line driving circuit which generates gray-scale voltages corresponding to display data, and applies the gray-scale voltages to a display panel; and to a display control circuit which outputs display data and control signals (sync signals, clock signals, and the-like) to a data line driving circuit.
More particularly, the present invention relates to a data line driving circuit and a display control circuit for a liquid crystal display, an organic EL (electroluminescent) display, a plasma display, a field emission display, and the like.
As a conventional technique, International Publication No. W099/63513 (Published Japanese Translation of PCT international publication for Patent Application No. 2002-517790) discloses a display driving system. This system comprises: a serial-to-parallel converter for rearranging segments of serially supplied digital pixel data into parallel pixel data; six digital-to-analog (D/A) converters for converting parallel pixel data of two pixels at a time into analog red, green and blue signals; plural column drivers each including an analog sample-and-hold module which samples six analog signals at the same time; and a timing controller for supplying an entire row of digital pixel data to the plural column drivers at the same time.
Further, Japanese Patent Application Laid-Open No. Hei 5-80722 publication discloses a liquid crystal display device. This liquid crystal display device has M multi-gray-scale driving circuits. The M multi-gray-scale driving circuits are each assigned to respective ones of M groups of pixel sections into which pixels contained in one horizontal row among pixels arranged in a matrix fashion are divided, and each apply display data to pixel sections of corresponding ones of the M groups in one horizontal row (M is an integer). The M multi-gray-scale driving circuits are arranged in a horizontal direction, and each of them includes a latch circuit, a digital-to-analog (D/A) converter, and a sample-and-hold circuit. The latch circuit sequentially takes in and temporarily stores digital display data for pixels corresponding to a horizontal pixel row divided by (M×N), obtained by subdividing the display data of each of the M groups of pixel sections into N groups (N is an integer). Every time when the digital display data for pixels corresponding to a horizontal pixel row divided by (M×N) is entered, the digital-to-analog (D/A) converter converts the digital display data into analog display data. The sample-and-hold circuit takes in the analog display data for pixels corresponding to the horizontal pixel row divided by M. After all the M multi-gray-scale driving circuits have taken in their corresponding analog display data for pixels corresponding to the horizontal pixel row divided by M, they apply the analog display data for the entire horizontal pixel row to the pixel sections at the same time.
In the above conventional technique, one multi-gray-scale driving circuit (column driver) employs a D/A converter whose capacity is smaller than that required for the analog display data simultaneously applied to the display pixel sections by that circuit (column driver), i.e., the number of D/A converters is smaller, and therefore the multi-gray-scale driving circuit (column driver) can be made compact.